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Groups |
Part |
Description |
Datasheet
Revision Date |
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C-16C5x |
The
C-16C5x core is the HDL model of the
Microchip Technology™ PIC16C5x 8-bit
micro controller. The PIC16C5x is a
family of 8-bit, ROM based
micro-controllers with a RISC
architecture inside. |
Rev. 08/2004
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C-8051 |
The C-8051core is the HDL
model of the Intel™ 8-bit 8051 micro
controller. The model is fully
compatible with the Intel 8051 standard.
Usually Aldec delivers both EDIF and
VHDL netlists for customers who order
the synthesizable model. The EDIF
netlist is used for the place and route
process and VHDL is the post-synthesis
netlist used for the simulation only.
Both netlists are technology-dependent
because they are created after the
synthesis where the customer needs to
specify a vendor, target family, etc.
Aldec can provide source code a set of
HDL testbenches for the cores. |
Rev. 08/2004
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C-8051S |
C-8051S soft core is
instruction set compatible with the
8051/52 8-bit micro-controller
architecture and can achieve average
performance of up to 20 million
instructions per second in today's FPGA
circuit technologies. It executed
instruction on 2-4 clock cycles. |
Rev. 08/2004
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C-8052S |
C-8052S soft core is
instruction set compatible with the
8051/52 8-bit micro-controller
architecture and can achieve average
performance of up to 20 million
instructions per second in today's FPGA
circuit technologies. It executed
instruction on 2-4 clock cycles. |
Rev. 08/2004
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C-DCT |
C-DCT soft core is the
unit to perform the Discrete Cosine
Transform (IDCT). It performs
two-dimensional 8 by 8 point DCT for the
period of 64 clock cycles in pipelined
mode. The characteristics of the DCT
make it extremely suited for image
compression algorithms. |
Rev. 08/2004
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C-DES |
The C-DES core is the HDL
model of the processor that performs DES
encryption and decryption. The model is
fully compliant with FIPS 46-2. |
Rev. 08/2004
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C-IDCT |
C-IDCT soft core is the
unit to perform the Inverse Discrete
Cosine Transform (IDCT). It performs
two-dimensional 8 by 8 point IDCT for
the period of 64 clock cycles in
pipelined mode. |
Rev. 08/2004
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C-SHA |
The C-SHA
core is the HDL model of the processor
that performs SHA-1 hash function
calculation. The model is fully
compliant with FIPS180-1. The core has
been synthesized and implemented to
different types of reprogrammable
devices. The model has been verified
using the simulation environment and
tested on the real hardware. |
Rev. 08/2004
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C-USB1 |
Aldec USB 1.1 core is
the HDL model of USB Function
Controller, which is fully compatible
with the USB 1.1 specification. The core
has been optimized for popular FPGA
devices and its functionality has been
verified in the real hardware. |
Rev. 08/2004
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C-USB2 |
Aldec USB 2.0 core is
the HDL model of USB Function
Controller, which is fully compatible
with the USB 2.0 specification. The core
has been optimized for popular FPGA
devices and its functionality has been
verified in the real hardware. |
Rev. 08/2004
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C-Viterbi |
The VHDL model of Viterbi
encoder/decoder. Viterbi encoding is
widely used for satellite and other
noisy communications channels. There are
two important components of a channel
using Viterbi encoding: the Viterib
encoder (at the transmitter), & the
Viterbi decoder (at the receiver). A
Viterbi decoder performs a maximum
likelihood detection of 1 bit data
transmitted over a channel with
inter-symbol interference (ISI). |
Rev. 08/2004
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C-8243 |
The C-8243 core is the
HDL model of the Intel™ 8243
input/output expander. |
Rev. 08/2004
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C-8253 |
The C-8253 core is the
HDL model of the Intel™ programmable
counter/timer device designed for use as
an Intel microcomputer peripheral. Has 4
read/write data modes & independent
software work mode programming for each
counter. |
Rev. 08/2004
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C-8254 |
The C-8254 core is the
HDL model of the Intel™ programmable
counter/timer device designed for use as
an Intel microcomputer peripheral. |
Rev. 08/2004
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C-8279 |
The AL8279 core is the
HDL model of the Intel™ 8279
Programmable Keyboard/Display Interface
device designed for use with Intel
microprocessors. The keyboard portion
provides a scanned interface to
64-contact key matrix while the display
portion provides an interface for
popular display technologies (e.g. LED). |
Rev. 08/2004
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C-FFT |
C-FFT soft core is the
unit to perform the Fast Fourier
Transform (FFT). It performs one
dimensional N -point radix two FFT,
where N = 16, 32, 64, 128, 256, 512,
1024, 2048. The data and coefficient
widths are tunable in the range 8 to 16. |
Rev. 08/2004
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